Sciweavers

85 search results - page 15 / 17
» High Data Rate 8-Bit Crypto Processor
Sort
View
ASPLOS
2009
ACM
14 years 8 months ago
StreamRay: a stream filtering architecture for coherent ray tracing
The wide availability of commodity graphics processors has made real-time graphics an intrinsic component of the human/computer interface. These graphics cores accelerate the z-bu...
Karthik Ramani, Christiaan P. Gribble, Al Davis
FCCM
1997
IEEE
103views VLSI» more  FCCM 1997»
13 years 11 months ago
An FPGA architecture for DRAM-based systolic computations
We propose an FPGA chip architecture based on a conventional FPGA logic array core, in which I/O pins are clocked at a much higher rate than that of the logic array that they serv...
Norman Margolus
ISCA
2011
IEEE
269views Hardware» more  ISCA 2011»
12 years 11 months ago
Power management of online data-intensive services
Much of the success of the Internet services model can be attributed to the popularity of a class of workloads that we call Online Data-Intensive (OLDI) services. These workloads ...
David Meisner, Christopher M. Sadler, Luiz Andr&ea...
DAC
2002
ACM
14 years 8 months ago
Design of a high-throughput low-power IS95 Viterbi decoder
The design of high-throughput large-state Viterbi decoders relies on the use of multiple arithmetic units. The global communication channels among these parallel processors often ...
Xun Liu, Marios C. Papaefthymiou
ICS
2009
Tsinghua U.
14 years 1 days ago
A comprehensive power-performance model for NoCs with multi-flit channel buffers
Large Multi-Processor Systems-on-Chip use Networks-on-Chip with a high degree of reusability and scalability for message communication. Therefore, network infrastructure is a cruc...
Mohammad Arjomand, Hamid Sarbazi-Azad