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ISSS
1995
IEEE
161views Hardware» more  ISSS 1995»
14 years 4 days ago
Synthesis of pipelined DSP accelerators with dynamic scheduling
To construct complete systems on silicon, application speci c DSP accelerators are needed to speed up the execution of high throughput DSP algorithms. In this paper, a methodology...
Patrick Schaumont, Bart Vanthournout, Ivo Bolsens,...
PATMOS
2010
Springer
13 years 6 months ago
L1 Data Cache Power Reduction Using a Forwarding Predictor
In most modern processor designs the L1 data cache has become a major consumer of power due to its increasing size and high frequency access rate. In order to reduce this power con...
P. Carazo, R. Apolloni, Fernando Castro, Daniel Ch...
NCA
2005
IEEE
14 years 2 months ago
Leveraging the Multiprocessing Capabilities of Modern Network Processors for Cryptographic Acceleration
The Kasumi block cipher provides integrity and confidentiality services for 3G wireless networks, but it also forms a bottleneck due to its computational overhead. Especially in ...
Gunnar Gaubatz, Berk Sunar
TC
2002
13 years 8 months ago
On Augmenting Trace Cache for High-Bandwidth Value Prediction
Value prediction is a technique that breaks true data dependences by predicting the outcome of an instruction and speculatively executes its data-dependent instructions based on th...
Sang Jeong Lee, Pen-Chung Yew
IPPS
2000
IEEE
14 years 1 months ago
MAJC-5200: A High Performance Microprocessor for Multimedia Computing
The newly introduced Microprocessor Architecture for Java Computing MAJC supports parallelism in a hierarchy of levels: multiprocessors on chip,vertical micro threading, instruct...
Subramania Sudharsanan