28 search results - page 5 / 6 » High Level Synthesis Of Multi-Precision Data Flow Graphs |
ASPDAC
2008
ACM
13 years 9 months ago
2008
ACM
We propose REWIRED (REgister Write Inhibition by REsource Dedication), a technique for reducing power during high level synthesis (HLS) by selectively inhibiting the storage of fun...
EUROPAR
2009
Springer
13 years 11 months ago
2009
Springer
A high-level understanding of how an application executes and which performance characteristics it exhibits is essential in many areas of high performance computing, such as applic...
ICCAD
1994
IEEE
13 years 11 months ago
1994
IEEE
In high level synthesis each node of a synchronous dataflow graph (DFG) is scheduled to a specific time and allocated to a processor. In this paper we present new integer linear p...
HPCN
2000
Springer
13 years 10 months ago
2000
Springer
Data futures in a metacomputing system refer to data products that have not yet been created but which can be uniquely named and manipulated. We employ data flow mechanisms expres...
VLSI
2005
Springer
14 years 15 days ago
2005
Springer
Quasi delay insensitive circuits are functionally independent of delays in gates and wires (except for some particular wires). Such asynchronous circuits offer high robustness but...