88 search results - page 6 / 18 » High Level Synthesis from Sim-nML Processor Models |
IPPS
2005
IEEE
14 years 1 months ago
2005
IEEE
The problem of writing high performance parallel applications becomes even more challenging when irregular, sparse or adaptive methods are employed. In this paper we introduce com...
DATE
2009
IEEE
14 years 2 months ago
2009
IEEE
Abstract—The demand for embedded computing power is continuously increasing and FPGAs are becoming very interesting computing platforms, as they provide huge amounts of customiza...
ICCD
2005
IEEE
14 years 4 months ago
2005
IEEE
Presently, Architecture Description Languages (ADLs) are widely used to raise the abstraction level of the design space exploration of Application Specific Instruction-set Proces...
SAFECOMP
2005
Springer
14 years 1 months ago
2005
Springer
In the telecommunications sector product development must minimise time to market while delivering high levels of dependability, availability, maintainability and scalability. High...
FCCM
2011
IEEE
12 years 11 months ago
2011
IEEE
— This paper describes an architecture and FPGA synthesis toolchain for building specialized, energy-saving coprocessors called Irregular Code Energy Reducers (ICERs) for a wide ...