249 search results - page 10 / 50 » High Level Synthesis of Timed Asynchronous Circuits |
ICES
2003
Springer
14 years 26 days ago
2003
Springer
This paper presents a methodology to design optimized electronic systems from high abstraction level descriptions. The methodology uses Genetic Programming in addition to high-leve...
IPPS
2007
IEEE
14 years 1 months ago
2007
IEEE
VLSID
1994
IEEE
13 years 11 months ago
1994
IEEE
In this paper, we present a formal analysis of the constraints of the scheduling problem, and evaluate the structure of the scheduling polytope described by those constraints. Pol...
CORR
2006
Springer
13 years 7 months ago
2006
Springer
The design of complex Systems-on-Chips implies to take into account communication and memory access constraints for the integration of dedicated hardware accelerator. In this paper...
ISVLSI
2002
IEEE
14 years 17 days ago
2002
IEEE
Timed Shannon circuits have been proposed as a synthesis approach for a low power optimization technique at the logic level since overall circuit switching probabilities may be re...