249 search results - page 11 / 50 » High Level Synthesis of Timed Asynchronous Circuits |
DATE
2003
IEEE
14 years 29 days ago
2003
IEEE
We present a high-level synthesis algorithm solving the combined scheduling, allocation and binding problem minimizing area under both latency and maximum power per clock-cycle co...
DATE
2000
IEEE
14 years 2 days ago
2000
IEEE
This paper presents a methodology towards synthesis of high performance analog circuits. Layout parasitics are estimated and compensated during circuit sizing. Physical layout con...
ASYNC
2000
IEEE
14 years 2 days ago
2000
IEEE
New design technologies rely on truly reusable IP blocks with simple means of assembly. Asynchronous methodologies could be a promising option to implement these requirements. Pro...
CAV
2008
Springer
13 years 9 months ago
2008
Springer
The growing design-productivity gap has made designers shift toward using high-level languages like C, C++ and Java to do system-level design. High-Level Synthesis (HLS) is the pro...
TCAD
2010
13 years 2 months ago
2010
The growing complexity of systems and their implementation into silicon encourages designers to look for model designs at higher levels of abstraction and then incrementally build ...