249 search results - page 15 / 50 » High Level Synthesis of Timed Asynchronous Circuits |
DAC
1999
ACM
14 years 8 months ago
1999
ACM
In this paper, we establish a theoretical framework for a new concept of scheduling called soft scheduling. In contrasts to the traditional schedulers referred as hard schedulers,...
DAC
1989
ACM
13 years 11 months ago
1989
ACM
- New algorithms for high-level synthesis are presented. The first performs scheduling under hardware resource constraints and improves on commonly used list scheduling techniques ...
VLSID
2003
IEEE
14 years 8 months ago
2003
IEEE
In this paper, we describe two new algorithms for datapath scheduling which aim at energy reduction while maintaining performance. The proposed algorithms, time constrained and re...
ASYNC
2000
IEEE
14 years 2 days ago
2000
IEEE
Fault Abstraction and Collapsing Framework for Asynchronous Circuits Philip P. Shirvani, Subhasish Mitra Center for Reliable Computing Stanford University Stanford, CA Jo C. Eberge...
ICCAD
2006
IEEE
14 years 4 months ago
2006
IEEE
Abstract— Chip-package thermal analysis is necessary for the design and synthesis of reliable, high-performance, low-power, compact integrated circuits (ICs). Many methods of IC ...