249 search results - page 19 / 50 » High Level Synthesis of Timed Asynchronous Circuits |
ISQED
2005
IEEE
14 years 1 months ago
2005
IEEE
Abstract— Reliability enhancements are traditionally implemented through redundancies at the system level or through the use of harden-cell-designs at the circuit level. Reliabil...
CCL
1994
Springer
13 years 11 months ago
1994
Springer
Abstract: This paper describes the application of CLP (constraint logic programming) to several digital circuit design problems. It is shown that logic programming together with ef...
ISSS
1996
IEEE
13 years 12 months ago
1996
IEEE
In this paper we discuss, what breakpoints in Source Level Emulationa are, how we can work with them and how we have to change the cicuit generated by high level synthesis to do s...
ICCAD
2001
IEEE
14 years 4 months ago
2001
IEEE
: This paper describes ASF, a novel cell-level analog synthesis framework that can size and bias a given circuit topology subject to a set of performance objectives and a manufactu...
FMCAD
2008
Springer
13 years 9 months ago
2008
Springer
Abstract--This paper presents the verification of an asynchronous arbiter modeled at the circuit level with non-linear ordinary differential equations. We use Brockett's annul...