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» High Level Synthesis of Timed Asynchronous Circuits
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DAC
2008
ACM
14 years 8 months ago
The synthesis of robust polynomial arithmetic with stochastic logic
As integrated circuit technology plumbs ever greater depths in the scaling of feature sizes, maintaining the paradigm of deterministic Boolean computation is increasingly challeng...
Weikang Qian, Marc D. Riedel
FPGA
2010
ACM
182views FPGA» more  FPGA 2010»
13 years 5 months ago
A comprehensive approach to modeling, characterizing and optimizing for metastability in FPGAs
Metastability is a phenomenon that can cause system failures in digital circuits. It may occur whenever signals are being transmitted across asynchronous or unrelated clock domain...
Doris Chen, Deshanand Singh, Jeffrey Chromczak, Da...
ASPDAC
2009
ACM
152views Hardware» more  ASPDAC 2009»
14 years 2 months ago
A novel Toffoli network synthesis algorithm for reversible logic
—Reversible logic studies have promising potential on energy lossless circuit design, quantum computation, nanotechnology, etc. Reversible logic features a one-to-one input outpu...
Yexin Zheng, Chao Huang
FASE
2000
Springer
13 years 11 months ago
Parallel Refinement Mechanisms for Real-Time Systems
This paper discusses highly general mechanisms for specifying the refinement of a real-time system as a collection of lower level parallel components that preserve the timing and f...
Paul Z. Kolano, Richard A. Kemmerer, Dino Mandriol...
ISSS
1996
IEEE
102views Hardware» more  ISSS 1996»
13 years 12 months ago
Throughput Optimization in Disk-Based Real-Time Application Specific Systems
Traditionally, application specific computations have been focusing on numerically intensive data manipulation. Modern communications and DSP applications, such as WWW, interactiv...
Stephen Docy, Inki Hong, Miodrag Potkonjak