249 search results - page 39 / 50 » High Level Synthesis of Timed Asynchronous Circuits |
FPL
2005
Springer
14 years 1 months ago
2005
Springer
This paper describes novel data-path architecture for FPGA-based multimedia processors. The proposed circuit can adapt itself at run-time to different operations and data wordleng...
ISCAS
2006
IEEE
14 years 1 months ago
2006
IEEE
—This paper introduces a technique to measure and adjust the relative phase of on-chip high speed digital signals using a random sampling technique of inferential statistics. The...
VLSID
2003
IEEE
14 years 8 months ago
2003
IEEE
Design of efficient System-on-Chips (SoCs) require thorough application analysis to identify various compute intensive parts. These compute intensive parts can be mapped to hardwa...
DATE
2007
IEEE
14 years 2 months ago
2007
IEEE
Design closure becomes hard to achieve at physical layout stage due to the emergence of long global interconnects. Consequently, interconnect planning needs to be integrated in hi...
ISCAS
2005
IEEE
14 years 1 months ago
2005
IEEE
Abstract— This paper presents and evaluates a hybrid implementation of a low complexity algorithm for speech enhancement, the Adaptive Gain Equalizer (AGE). The AGE is a subband ...