249 search results - page 9 / 50 » High Level Synthesis of Timed Asynchronous Circuits |
VTS
1999
IEEE
13 years 12 months ago
1999
IEEE
High-level test pattern generation is today a widely investigated research topic. The present paper proposes a fully automated, simulation-based ATPG system, to address test patte...
ACSD
2005
IEEE
14 years 1 months ago
2005
IEEE
Register Transfer Level (RTL) synthesis model which simplified the design of clocked circuits allowed design automation boost and VLSI progress for more than a decade. Shrinking t...
DATE
2005
IEEE
14 years 1 months ago
2005
IEEE
This paper presents the novel idea of multi-placement structures, for a fast and optimized placement instantiation in analog circuit synthesis. These structures need to be generat...
ISSS
1997
IEEE
13 years 12 months ago
1997
IEEE
This paper presents a novel source-level dynamic analysis methodology and tool for High-Level Synthesis (HLS). It not only for the first time enables HLS to offer source-level de...
CASES
2007
ACM
13 years 11 months ago
2007
ACM
The development of robust and efficient synthesis tools is important if asynchronous design is to gain more widespread acceptance. Syntax-directed translation is a powerful synthe...