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DATE
2008
IEEE
112views Hardware» more  DATE 2008»
14 years 5 months ago
An novel Methodology for Reducing SoC Test Data Volume on FPGA-based Testers
Low-Cost test methodologies for Systems-on-Chip are increasingly popular. They dictate which features have to be included on-chip and which test procedures have to be adopted in o...
Paolo Bernardi, Matteo Sonza Reorda
MICRO
2008
IEEE
139views Hardware» more  MICRO 2008»
14 years 5 months ago
Adaptive data compression for high-performance low-power on-chip networks
With the recent design shift towards increasing the number of processing elements in a chip, high-bandwidth support in on-chip interconnect is essential for low-latency communicat...
Yuho Jin, Ki Hwan Yum, Eun Jung Kim
SEUS
2008
IEEE
14 years 5 months ago
Model Based Synthesis of Embedded Software
Abstract— This paper presents SW synthesis using Embedded System Environment (ESE), a tool set for design of multicore embedded systems. We propose a classification of multicore...
Daniel D. Gajski, Samar Abdi, Ines Viskic
DASFAA
2007
IEEE
187views Database» more  DASFAA 2007»
14 years 5 months ago
OntoDB: An Ontology-Based Database for Data Intensive Applications
Recently, several approaches and systems were proposed to store in the same database data and the ontologies describing their meanings. We call these databases, ontology-based data...
Dehainsala Hondjack, Guy Pierra, Ladjel Bellatrech...
DSN
2007
IEEE
14 years 5 months ago
BlackJack: Hard Error Detection with Redundant Threads on SMT
Testing is a difficult process that becomes more difficult with scaling. With smaller and faster devices, tolerance for errors shrinks and devices may act correctly under certain ...
Ethan Schuchman, T. N. Vijaykumar