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ICCD
2002
IEEE
110views Hardware» more  ICCD 2002»
14 years 6 months ago
Branch Predictor Prediction: A Power-Aware Branch Predictor for High-Performance Processors
We introduce Branch Predictor Prediction (BPP) as a power-aware branch prediction technique for high performance processors. Our predictor reduces branch prediction power dissipat...
Amirali Baniasadi, Andreas Moshovos
IEEEPACT
2002
IEEE
14 years 2 months ago
Optimizing Loop Performance for Clustered VLIW Architectures
Modern embedded systems often require high degrees of instruction-level parallelism (ILP) within strict constraints on power consumption and chip cost. Unfortunately, a high-perfo...
Yi Qian, Steve Carr, Philip H. Sweany
MICRO
2009
IEEE
121views Hardware» more  MICRO 2009»
14 years 4 months ago
Improving memory bank-level parallelism in the presence of prefetching
DRAM systems achieve high performance when all DRAM banks are busy servicing useful memory requests. The degree to which DRAM banks are busy is called DRAM Bank-Level Parallelism ...
Chang Joo Lee, Veynu Narasiman, Onur Mutlu, Yale N...
ISCAS
1999
IEEE
70views Hardware» more  ISCAS 1999»
14 years 2 months ago
On optimization of filter banks with denoising applications
The problem of optimization of subband coders for given input statistics has received considerable attention in recent literature. The goal in these works has been to maximize the...
Sony Akkarakaran, P. P. Vaidyanathan
ICDAR
2003
IEEE
14 years 3 months ago
Automatic Segmentation and Recognition System for Handwritten Dates on Canadian Bank Cheques
This paper describes a system being developed to recognize date information handwritten on Canadian bank cheques. A segmentation based strategy is adopted in this system. In order...
Qizhi Xu, Louisa Lam, Ching Y. Suen