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COORDINATION
2009
Springer
14 years 8 months ago
High-Performance Transactional Event Processing
This paper presents a transactional framework for low-latency, high-performance, concurrent event processing in Java. At the heart of our framework lies Reflexes, a restricted prog...
Antonio Cunei, Rachid Guerraoui, Jesper Honig Spri...
DATE
2005
IEEE
118views Hardware» more  DATE 2005»
14 years 1 months ago
Energy- and Performance-Driven NoC Communication Architecture Synthesis Using a Decomposition Approach
In this paper, we present a methodology for customized communication architecture synthesis that matches the communication requirements of the target application. This is an impor...
Ümit Y. Ogras, Radu Marculescu
DAC
2001
ACM
14 years 8 months ago
LOTTERYBUS: A New High-Performance Communication Architecture for System-on-Chip Designs
This paper presents LOTTERYBUS, a novel high-performance communication architecture for system-on-chip (SoC) designs. The LOTTERYBUS architecture was designed to address the follo...
Kanishka Lahiri, Anand Raghunathan, Ganesh Lakshmi...
ICMCS
2007
IEEE
144views Multimedia» more  ICMCS 2007»
14 years 1 months ago
A Framework for Modular Signal Processing Systems with High-Performance Requirements
This paper introduces the software framework MMER Lab which allows an effective assembly of modular signal processing systems optimized for memory efficiency and performance. Our...
Lukas Diduch, Ronald Müller, Gerhard Rigoll
IEEEPACT
2007
IEEE
14 years 1 months ago
Performance Portable Optimizations for Loops Containing Communication Operations
Effective use of communication networks is critical to the performance and scalability of parallel applications. Partitioned Global Address Space languages like UPC bring the pro...
Costin Iancu, Wei Chen, Katherine A. Yelick