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DAC
2001
ACM
16 years 5 months ago
LOTTERYBUS: A New High-Performance Communication Architecture for System-on-Chip Designs
This paper presents LOTTERYBUS, a novel high-performance communication architecture for system-on-chip (SoC) designs. The LOTTERYBUS architecture was designed to address the follo...
Kanishka Lahiri, Anand Raghunathan, Ganesh Lakshmi...
SSD
2005
Springer
145views Database» more  SSD 2005»
15 years 9 months ago
High Performance Multimodal Networks
Networks often form the core of many users’ spatial databases. Networks are used to support the rapid navigation and analysis of linearly connected data such as that found in tra...
Erik G. Hoel, Wee-Liang Heng, Dale Honeycutt
SBACPAD
2006
IEEE
147views Hardware» more  SBACPAD 2006»
15 years 10 months ago
Controlling the Power and Area of Neural Branch Predictors for Practical Implementation in High-Performance Processors
Neural-inspired branch predictors achieve very low branch misprediction rates. However, previously proposed implementations have a variety of characteristics that make them challe...
Daniel A. Jiménez, Gabriel H. Loh
HPCN
1997
Springer
15 years 8 months ago
Parallel Solution of Irregular, Sparse Matrix Problems Using High Performance Fortran
For regular, sparse, linear systems, like those derived from regular grids, using High Performance Fortran (HPF) for iterative solvers is straightforward. However, for irregular ma...
Eric de Sturler, Damian Loher
133
Voted
TC
2010
15 years 2 months ago
Architecture Exploration of High-Performance PCs with a Solid-State Disk
—As the cost per bit of NAND flash memory devices rapidly decreases, NAND-flash-based Solid-State Disks (SSDs) are replacing Hard Disk Drives (HDDs) used in a wide spectrum of co...
Dong Kim, Kwanhu Bang, Seung-Hwan Ha, Sungroh Yoon...