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CCGRID
2005
IEEE
15 years 10 months ago
A batch scheduler with high level components
In this article we present the design choices and the evaluation of a batch scheduler for large clusters, named OAR. This batch scheduler is based upon an original design that emp...
Nicolas Capit, Georges Da Costa, Yiannis Georgiou,...
IPPS
2010
IEEE
15 years 2 months ago
BlobSeer: Bringing high throughput under heavy concurrency to Hadoop Map-Reduce applications
Hadoop is a software framework supporting the Map/Reduce programming model. It relies on the Hadoop Distributed File System (HDFS) as its primary storage system. The efficiency of ...
Bogdan Nicolae, Diana Moise, Gabriel Antoniu, Luc ...
IPPS
2007
IEEE
15 years 10 months ago
Speculative Flow Control for High-Radix Datacenter Interconnect Routers
High-radix switches are desirable building blocks for large computer interconnection networks, because they are more suitable to convert chip I/O bandwidth into low latency and lo...
Cyriel Minkenberg, Mitchell Gusat
MASCOTS
2004
15 years 5 months ago
Design and Implementation of a High Speed Microprocessor Simulator BurstScalar
This paper describes the design and implementation of our high speed simulator for out-of-order microprocessors named BurstScalar. The simulator is based on the wellknown SimpleSc...
Takashi Nakada, Hiroshi Nakashima
IPPS
2007
IEEE
15 years 10 months ago
A Portable Framework for High-Speed Parallel Producer/Consumers on Real CMP, SMT and SMP Architectures
This paper explores generating efficient, portable HighSpeed Producer Consumer (HSPC) code on current shared memory architectures: Chip Multi-Processors (CMP), Simultaneous Multi...
Richard T. Saunders, Clinton L. Jeffery, Derek T. ...