Sciweavers

174 search results - page 26 / 35
» High Performance FPGA Implementation of the Mersenne Twister
Sort
View
ASAP
2007
IEEE
104views Hardware» more  ASAP 2007»
13 years 9 months ago
Hardware Acceleration for 3-D Radiation Dose Calculation
Abstract— The problem of calculating accurate dose distributions lies in the heart of modern radiation therapy for cancer treatment. Software implementations of dose calculation ...
Bo Zhou, Xiaobo Sharon Hu, Danny Z. Chen, Cedric X...
ICC
2011
IEEE
237views Communications» more  ICC 2011»
12 years 7 months ago
Reorganized and Compact DFA for Efficient Regular Expression Matching
—Regular expression matching has become a critical yet challenging technique in content-aware network processing, such as application identification and deep inspection. To meet ...
Kai Wang, Yaxuan Qi, Yibo Xue, Jun Li
FPGA
2005
ACM
195views FPGA» more  FPGA 2005»
14 years 1 months ago
Sparse Matrix-Vector multiplication on FPGAs
Floating-point Sparse Matrix-Vector Multiplication (SpMXV) is a key computational kernel in scientific and engineering applications. The poor data locality of sparse matrices sig...
Ling Zhuo, Viktor K. Prasanna
ARC
2008
Springer
104views Hardware» more  ARC 2008»
13 years 9 months ago
PARO: Synthesis of Hardware Accelerators for Multi-Dimensional Dataflow-Intensive Applications
Abstract. In this paper, we present the PARO design tool for the automated hardware synthesis of massively parallel embedded architectures for given dataflow dominant applications....
Frank Hannig, Holger Ruckdeschel, Hritam Dutta, J&...
FCCM
2003
IEEE
148views VLSI» more  FCCM 2003»
14 years 23 days ago
A Hardware Gaussian Noise Generator for Channel Code Evaluation
Hardware simulation of channel codes offers the potential of improving code evaluation speed by orders of magnitude over workstation- or PC-based simulation. We describe a hardwar...
Dong-U Lee, Wayne Luk, John D. Villasenor, Peter Y...