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ISCAS
2005
IEEE
132views Hardware» more  ISCAS 2005»
14 years 1 months ago
A high performance distributed-parallel-processor architecture for 3D IIR digital filters
—Real-time spatio-temporal VLSI 3D IIR digital filters may be used for imaging or beamforming applications employing 3D input signals from synchronously-sampled multi-sensor arra...
Arjuna Madanayake, Leonard T. Bruton
IPPS
2000
IEEE
14 years 6 days ago
MAJC-5200: A High Performance Microprocessor for Multimedia Computing
The newly introduced Microprocessor Architecture for Java Computing MAJC supports parallelism in a hierarchy of levels: multiprocessors on chip,vertical micro threading, instruct...
Subramania Sudharsanan
CORR
2011
Springer
197views Education» more  CORR 2011»
13 years 2 months ago
High-Throughput Transaction Executions on Graphics Processors
OLTP (On-Line Transaction Processing) is an important business system sector in various traditional and emerging online services. Due to the increasing number of users, OLTP syste...
Bingsheng He, Jeffrey Xu Yu
ARC
2008
Springer
104views Hardware» more  ARC 2008»
13 years 9 months ago
PARO: Synthesis of Hardware Accelerators for Multi-Dimensional Dataflow-Intensive Applications
Abstract. In this paper, we present the PARO design tool for the automated hardware synthesis of massively parallel embedded architectures for given dataflow dominant applications....
Frank Hannig, Holger Ruckdeschel, Hritam Dutta, J&...
DAMON
2007
Springer
14 years 2 months ago
In-memory grid files on graphics processors
Recently, graphics processing units, or GPUs, have become a viable alternative as commodity, parallel hardware for generalpurpose computing, due to their massive data-parallelism,...
Ke Yang, Bingsheng He, Rui Fang, Mian Lu, Naga K. ...