624 search results - page 18 / 125 » High Performance Matrix Multiplication on Many Cores |
ISPASS
2007
IEEE
14 years 2 months ago
2007
IEEE
This paper proposes a specialized memory structure called CA-RAM (Content Addressable Random Access Memory) to accelerate search operations present in many important real-world ap...
ISCA
2011
IEEE
12 years 11 months ago
2011
IEEE
A growing body of work has compiled a strong case for the single-ISA heterogeneous multi-core paradigm. A single-ISA heterogeneous multi-core provides multiple, differently-design...
NIPS
2007
13 years 9 months ago
2007
Many existing approaches to collaborative filtering can neither handle very large datasets nor easily deal with users who have very few ratings. In this paper we present the Prob...
ISCAS
2007
IEEE
14 years 2 months ago
2007
IEEE
Abstract— A low-density parity-check (LDPC) decoder architecture that supports variable block sizes and multiple code rates is presented. The proposed architecture is based on th...
ACMMSP
2006
ACM
14 years 1 months ago
2006
ACM
A blossoming paradigm for block-recursive matrix algorithms is presented that, at once, attains excellent performance measured by • time, • TLB misses, • L1 misses, • L2 m...