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» High Performance Matrix Multiplication on Many Cores
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ATS
2010
IEEE
250views Hardware» more  ATS 2010»
13 years 5 months ago
Efficient Embedding of Deterministic Test Data
Systems with many integrated circuits (ICs), often of the same type, are increasingly common to meet the constant performance demand. However, systems in recent semiconductor techn...
Mudassar Majeed, Daniel Ahlstrom, Urban Ingelsson,...
ICCD
2006
IEEE
132views Hardware» more  ICCD 2006»
14 years 6 months ago
FPGA-based Design of a Large Moduli Multiplier for Public Key Cryptographic Systems
— High secure cryptographic systems require large bit-length encryption keys which presents a challenge to their efficient hardware implementation especially in embedded devices...
Osama Al-Khaleel, Christos A. Papachristou, Franci...
BMCBI
2007
174views more  BMCBI 2007»
13 years 9 months ago
Normalization method for metabolomics data using optimal selection of multiple internal standards
Background: Success of metabolomics as the phenotyping platform largely depends on its ability to detect various sources of biological variability. Removal of platform-specific so...
Marko Sysi-Aho, Mikko Katajamaa, Laxman Yetukuri, ...
FPL
2004
Springer
171views Hardware» more  FPL 2004»
14 years 2 months ago
A Modular System for FPGA-Based TCP Flow Processing in High-Speed Networks
Field Programmable Gate Arrays (FPGAs) can be used in Intrusion Prevention Systems (IPS) to inspect application data contained within network flows. An IPS operating on high-speed...
David V. Schuehler, John W. Lockwood
ISCA
1995
IEEE
110views Hardware» more  ISCA 1995»
14 years 17 days ago
Optimization of Instruction Fetch Mechanisms for High Issue Rates
Recent superscalar processors issue four instructions per cycle. These processors are also powered by highly-parallel superscalar cores. The potential performance can only be expl...
Thomas M. Conte, Kishore N. Menezes, Patrick M. Mi...