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» High Performance Matrix Multiplication on Many Cores
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TPDS
2002
94views more  TPDS 2002»
13 years 7 months ago
Recursive Array Layouts and Fast Matrix Multiplication
The performance of both serial and parallel implementations of matrix multiplication is highly sensitive to memory system behavior. False sharing and cache conflicts cause traditi...
Siddhartha Chatterjee, Alvin R. Lebeck, Praveen K....
ISVLSI
2007
IEEE
100views VLSI» more  ISVLSI 2007»
14 years 2 months ago
Vector Processing Support for FPGA-Oriented High Performance Applications
In this paper, we propose and implement a vector processing system that includes two identical vector microprocessors embedded in two FPGA chips. Each vector microprocessor suppor...
Hongyan Yang, Shuai Wang, Sotirios G. Ziavras, Jie...
DATE
2003
IEEE
134views Hardware» more  DATE 2003»
14 years 1 months ago
A Multi-Level Design Flow for Incorporating IP Cores: Case Study of 1D Wavelet IP Integration
The design of high performance multimedia systems in a short time force us to use IP's blocks in many designs. However, their correct integration in a design implies more com...
Adel Baganne, Imed Bennour, Mehrez Elmarzougui, Ri...
BMCBI
2006
100views more  BMCBI 2006»
13 years 7 months ago
Using the nucleotide substitution rate matrix to detect horizontal gene transfer
Background: Horizontal gene transfer (HGT) has allowed bacteria to evolve many new capabilities. Because transferred genes perform many medically important functions, such as conf...
Micah Hamady, M. D. Betterton, Rob Knight
DAC
2008
ACM
14 years 8 months ago
Federation: repurposing scalar cores for out-of-order instruction issue
Future SoCs will contain multiple cores. For workloads with significant parallelism, prior work has shown the benefit of many small, multi-threaded, scalar cores. For workloads th...
David Tarjan, Michael Boyer, Kevin Skadron