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IEEEPACT
2008
IEEE
14 years 3 months ago
Skewed redundancy
Technology scaling in integrated circuits has consistently provided dramatic performance improvements in modern microprocessors. However, increasing device counts and decreasing o...
Gordon B. Bell, Mikko H. Lipasti
HPCA
2009
IEEE
14 years 9 months ago
Design and evaluation of a hierarchical on-chip interconnect for next-generation CMPs
Performance and power consumption of an on-chip interconnect that forms the backbone of Chip Multiprocessors (CMPs), are directly influenced by the underlying network topology. Bo...
Reetuparna Das, Soumya Eachempati, Asit K. Mishra,...
IEEEPACT
1998
IEEE
14 years 24 days ago
Static Methods in Hybrid Branch Prediction
Hybrid branch predictors combine the predictions of multiple single-level or two-level branch predictors. The prediction-combining hardware -- the "meta-predictor" -may ...
Dirk Grunwald, Donald C. Lindsay, Benjamin G. Zorn
ICS
1995
Tsinghua U.
14 years 3 days ago
A Data Cache with Multiple Caching Strategies Tuned to Different Types of Locality
Current data cache organizations fail to deliver high performance in scalar processors for many vector applications. There are two main reasons for this loss of performance: the u...
Antonio González, Carlos Aliagas, Mateo Val...
MICRO
1998
IEEE
79views Hardware» more  MICRO 1998»
14 years 24 days ago
Widening Resources: A Cost-effective Technique for Aggressive ILP Architectures
The inherent instruction-level parallelism (ILP) of current applications (specially those based on floating point computations) has driven hardware designers and compilers writers...
David López, Josep Llosa, Mateo Valero, Edu...