Sciweavers

57 search results - page 4 / 12
» High Speed Switch Scheduling for Local Area Networks
Sort
View
HIPEAC
2010
Springer
14 years 4 months ago
Low-Overhead, High-Speed Multi-core Barrier Synchronization
Whereas efficient barrier implementations were once a concern only in high-performance computing, recent trends in core integration make the topic relevant even for general-purpos...
John Sartori, Rakesh Kumar
GLOBECOM
2009
IEEE
13 years 11 months ago
Joint Channel and Echo Impulse Response Shortening for High-Speed Data Transmission
The unit-norm constraint optimization for joint shortening of channel and echo impulse response is presented in this paper. The optimization is performed in the mean-square sense (...
Ali Enteshari, Jarir M. Fadlullah, Mohsen Kavehrad
HPDC
1995
IEEE
13 years 11 months ago
A High Speed Implementation of Adaptive Shaping for Dynamic Bandwidth Allocation
Most algorithms proposed for controlling traffic prior to entering ATM networks are based on static mechanisms. Such static control mechanisms do not account for the dynamics of ...
Cameron Braun, V. Sirkay, H. Uriona, Srini W. Seet...
FCCM
2006
IEEE
131views VLSI» more  FCCM 2006»
14 years 1 months ago
Packet Switched vs. Time Multiplexed FPGA Overlay Networks
— Dedicated, spatially configured FPGA interconnect is efficient for applications that require high throughput connections between processing elements (PEs) but with a limited ...
Nachiket Kapre, Nikil Mehta, Michael DeLorimier, R...
IPPS
1998
IEEE
13 years 12 months ago
HIPIQS: A High-Performance Switch Architecture Using Input Queuing
Switch-based interconnects are used in a number of application domains including parallel system interconnects, local area networks, and wide area networks. However, very few swit...
Rajeev Sivaram, Craig B. Stunkel, Dhabaleswar K. P...