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» High level synthesis for reconfigurable datapath structures
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RSP
2005
IEEE
155views Control Systems» more  RSP 2005»
14 years 1 months ago
Optimization Techniques for ADL-Driven RTL Processor Synthesis
Nowadays, Architecture Description Languages (ADLs) are getting popular to speed up the development of complex SoC design, by performing the design space explon a higher level of ...
Oliver Schliebusch, Anupam Chattopadhyay, Ernst Ma...
ICES
2005
Springer
177views Hardware» more  ICES 2005»
14 years 1 months ago
Evolving Hardware by Dynamically Reconfiguring Xilinx FPGAs
Evolvable Hardware arises as a promising solution for automatic digital synthesis of digital and analog circuits. During the last decade, a special interest has been focused on evo...
Andres Upegui, Eduardo Sanchez
VLSID
2006
IEEE
183views VLSI» more  VLSID 2006»
14 years 1 months ago
Design Challenges for High Performance Nano-Technology
This tutorial present the key aspects of design challenges and its solutions that are being experienced in VLSI design in the era of nano technology. The focus will be on design c...
Goutam Debnath, Paul J. Thadikaran
FPL
2008
Springer
125views Hardware» more  FPL 2008»
13 years 9 months ago
Reconfigurable platforms and the challenges for large-scale implementations of spiking neural networks
FPGA devices have witnessed popularity in their use for the rapid prototyping of biological Spiking Neural Network (SNNs) applications, as they offer the key requirement of reconf...
Jim Harkin, Fearghal Morgan, Steve Hall, Piotr Dud...
VLSID
2007
IEEE
210views VLSI» more  VLSID 2007»
14 years 8 months ago
Dynamically Optimizing FPGA Applications by Monitoring Temperature and Workloads
In the past, Field Programmable Gate Array (FPGA) circuits only contained a limited amount of logic and operated at a low frequency. Few applications running on FPGAs consumed exc...
Phillip H. Jones, Young H. Cho, John W. Lockwood