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IWMM
2010
Springer
173views Hardware» more  IWMM 2010»
14 years 2 months ago
CETS: compiler enforced temporal safety for C
Temporal memory safety errors, such as dangling pointer dereferences and double frees, are a prevalent source of software bugs in unmanaged languages such as C. Existing schemes t...
Santosh Nagarakatte, Jianzhou Zhao, Milo M. K. Mar...
BMCBI
2007
158views more  BMCBI 2007»
13 years 9 months ago
Penalized likelihood for sparse contingency tables with an application to full-length cDNA libraries
Background: The joint analysis of several categorical variables is a common task in many areas of biology, and is becoming central to systems biology investigations whose goal is ...
Corinne Dahinden, Giovanni Parmigiani, Mark C. Eme...
BMCBI
2004
120views more  BMCBI 2004»
13 years 9 months ago
Optimal cDNA microarray design using expressed sequence tags for organisms with limited genomic information
Background: Expression microarrays are increasingly used to characterize environmental responses and hostparasite interactions for many different organisms. Probe selection for cD...
Yian A. Chen, David J. Mckillen, Shuyuan Wu, Matth...
ICCD
2006
IEEE
182views Hardware» more  ICCD 2006»
14 years 6 months ago
A performance and power analysis of WK-Recursive and Mesh Networks for Network-on-Chips
—Network-on-Chip (NoC) has been proposed as an attractive alternative to traditional dedicated wires to achieve high performance and modularity. Power efficiency is one of the mo...
Dara Rahmati, Abbas Eslami Kiasari, Shaahin Hessab...
VLSID
2003
IEEE
147views VLSI» more  VLSID 2003»
14 years 10 months ago
SoC Synthesis with Automatic Hardware Software Interface Generation
Design of efficient System-on-Chips (SoCs) require thorough application analysis to identify various compute intensive parts. These compute intensive parts can be mapped to hardwa...
Amarjeet Singh 0002, Amit Chhabra, Anup Gangwar, B...