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VLSID
2006
IEEE
150views VLSI» more  VLSID 2006»
14 years 10 months ago
A Comprehensive SoC Design Methodology for Nanometer Design Challenges
SoC design methodologies are under constant revision due to adoption of fast shrinking process technologies at nanometer levels. Nanometer process geometries exhibit new complex d...
R. Raghavendra Kumar, Ricky Bedi, Ramadas Rajagopa...
DATE
2008
IEEE
112views Hardware» more  DATE 2008»
14 years 4 months ago
An novel Methodology for Reducing SoC Test Data Volume on FPGA-based Testers
Low-Cost test methodologies for Systems-on-Chip are increasingly popular. They dictate which features have to be included on-chip and which test procedures have to be adopted in o...
Paolo Bernardi, Matteo Sonza Reorda
CSIE
2009
IEEE
14 years 1 months ago
An Efficient Mixed-Mode Execution Environment for C on Mobile Phone Platforms
Mobile devices are constrained in terms of computational power, battery lifetime and memory sizes. Software development for mobile devices is further complicated by application co...
Taekhoon Kim, Sungho Kim, Kirak Hong, Hwangho Kim,...
ICC
2007
IEEE
119views Communications» more  ICC 2007»
14 years 4 months ago
Performance Measurement, Evaluation and Analysis of Push-to-Talk in 3G Networks
— Push-to-talk over Cellular (PoC) is considered as one of important applications in Next Generation Networks (NGN). The main objective of this study is to investigate the perfor...
Wei-Peng Chen, Steven Licking, Takashi Ohno, Satos...
ASAP
2010
IEEE
138views Hardware» more  ASAP 2010»
13 years 11 months ago
Enhancing performance of network-on-chip architectures with millimeter-wave wireless interconnects
In a traditional Network-on-Chip (NoC), latency and power dissipation increase with system size due to its inherent multi-hop communications. The performance of NoC communication ...
Sujay Deb, Amlan Ganguly, Kevin Chang, Partha Prat...