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DSD
2006
IEEE
107views Hardware» more  DSD 2006»
14 years 3 months ago
A High Level Power Model for the Nostrum NoC
We propose a power model for the Nostrum NoC. For this purpose an empirical power model of links and switches has been formulated and validated with the Synopsys Power Compiler. T...
Sandro Penolazzi, Axel Jantsch
ISLPED
1996
ACM
68views Hardware» more  ISLPED 1996»
14 years 1 months ago
Energy-recovery CMOS for highly pipelined DSP designs
We compare the frequency-versus-power dissipation performance of two energy-recovery CMOS implementations to that of a conventional, supply-voltage-scaled design. The application ...
William C. Athas, W.-C. Liu, Lars J. Svensson
ICANN
2005
Springer
14 years 3 months ago
High-Throughput Multi-dimensional Scaling (HiT-MDS) for cDNA-Array Expression Data
Multidimensional Scaling (MDS) is a powerful dimension reduction technique for embedding high-dimensional data into a lowdimensional target space. Thereby, the distance relationshi...
Marc Strickert, Stefan Teichmann, Nese Sreenivasul...
FCCM
2000
IEEE
75views VLSI» more  FCCM 2000»
14 years 2 months ago
Stream-Oriented FPGA Computing in the Streams-C High Level Language
Maya Gokhale, Janice M. Stone, Jeffrey M. Arnold, ...