18572 search results - page 65 / 3715 » High performance C |
115
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HPN
1992
15 years 3 months ago
1992
This paper describes a new host interface architecture for high-speed networks operating at 800 of Mbit/second or higher rates. The architecture is targeted to achieve several 100...
113
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ANCS
2009
ACM
15 years 9 days ago
2009
ACM
This paper proposes a new server architecture EINIC (Enhanced Integrated NIC) for multi-core processors to tackle the mismatch between network speed and host computational capacit...
118
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TCOM
2010
14 years 9 months ago
2010
In this paper, we propose a new implementation of the Extended Min-Sum (EMS) decoder for non-binary LDPC codes. A particularity of the new algorithm is that it takes into accounts...
ICCD
2003
IEEE
15 years 11 months ago
2003
IEEE
108
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DSN
2005
IEEE
15 years 8 months ago
2005
IEEE
Register files are in the critical path of most high-performance processors and their latency is one of the most important factors that limit their size. Our goal is to develop er...