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IPPS
2002
IEEE
14 years 3 months ago
Variable Partitioning and Scheduling of Multiple Memory Architectures for DSP
Multiple memory module architecture enjoys higher memory access bandwidth and thus higher performance. Two key problems in gaining high performance in this kind of architecture ar...
Qingfeng Zhuge, Bin Xiao, Edwin Hsing-Mean Sha
DATE
2003
IEEE
102views Hardware» more  DATE 2003»
14 years 4 months ago
Power Constrained High-Level Synthesis of Battery Powered Digital Systems
We present a high-level synthesis algorithm solving the combined scheduling, allocation and binding problem minimizing area under both latency and maximum power per clock-cycle co...
S. F. Nielsen, Jan Madsen
GLVLSI
2000
IEEE
104views VLSI» more  GLVLSI 2000»
14 years 3 months ago
A new technique for estimating lower bounds on latency for high level synthesis
In this paper we present a novel and fast estimation technique that produces tight latency lower bounds for Data Flow Graphs representing time critical segments of the application...
Helvio P. Peixoto, Margarida F. Jacome
ANTSW
2004
Springer
14 years 2 months ago
Mesh-Partitioning with the Multiple Ant-Colony Algorithm
ed Abstract We present two heuristic mesh-partitioning methods, both of which build on the multiple ant-colony algorithm in order to improve the quality of the mesh partitions. The...
Peter Korosec, Jurij Silc, Borut Robic
PRL
2006
117views more  PRL 2006»
13 years 10 months ago
Improving image segmentation quality through effective region merging using a hierarchical social metaheuristic
This paper proposes a new evolutionary region merging method in order to efficiently improve segmentation quality results. Our approach starts from an oversegmented image, which is...
Abraham Duarte, Miguel Ángel Sánchez...