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FCCM
2008
IEEE
165views VLSI» more  FCCM 2008»
14 years 1 months ago
Performance Analysis with High-Level Languages for High-Performance Reconfigurable Computing
High-Level Languages (HLLs) for FPGAs (FieldProgrammable Gate Arrays) facilitate the use of reconfigurable computing resources for application developers by using familiar, higher...
John Curreri, Seth Koehler, Brian Holland, Alan D....
DAC
1994
ACM
13 years 11 months ago
Memory Estimation for High Level Synthesis
Abstract -- This paper describes a new memory estimation technique for DSP applications written in an applicative language. Since no concept of storage is present in an applicative...
Ingrid Verbauwhede, Chris J. Scheers, Jan M. Rabae...
TRETS
2010
142views more  TRETS 2010»
13 years 5 months ago
Performance Analysis Framework for High-Level Language Applications in Reconfigurable Computing
s, and abstractions, typically enabling faster development times than with traditional Hardware ion Languages (HDLs). However, programming at a higher level of abstraction is typic...
John Curreri, Seth Koehler, Alan D. George, Brian ...
WSC
2004
13 years 8 months ago
Implementing the High Level Architecture in the Virtual Test Bed
The Virtual Test Bed (VTB) is a prototype of a virtual engineering environment to study operations of current and future space vehicles, spaceports, and ranges. The HighLevel Arch...
José A. Sepúlveda, Luis C. Rabelo, J...
SECON
2007
IEEE
14 years 1 months ago
High-Level Application Development is Realistic for Wireless Sensor Networks
—Programming Wireless Sensor Network (WSN) applications is known to be a difficult task. Part of the problem is that the resource limitations of typical WSN nodes force programm...
Marcin Karpinski, Vinny Cahill