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FPL
2000
Springer
116views Hardware» more  FPL 2000»
14 years 1 months ago
High-Level Area and Performance Estimation of Hardware Building Blocks on FPGAs
Abstract. Field-programmable gate arrays (FPGAs) have become increasingly interesting in system design and due to the rapid technological progress ever larger devices are commercia...
Rolf Enzler, Tobias Jeger, Didier Cottet, Gerhard ...
HCI
2007
13 years 11 months ago
Tasks Models Merging for High-Level Component Composition
Abstract. As users become more and more demanding about the software environments they use, they need environments offering them the possibility to integrate new tools in response ...
Arnaud Lewandowski, Sophie Lepreux, Grégory...
VLSID
2009
IEEE
155views VLSI» more  VLSID 2009»
14 years 10 months ago
Unified Challenges in Nano-CMOS High-Level Synthesis
: The challenges in nano-CMOS circuit design include the following: variability, leakage, power, thermals, reliability, and yield. This talk will focus on interdependent considerat...
Saraju P. Mohanty
EUROSSC
2010
Springer
13 years 7 months ago
Identifying Important Action Primitives for High Level Activity Recognition
Smart homes have a user centered design that makes human activity as the most important type of context to adapt the environment according to people's needs. Sensor systems th...
Atif Manzoor, Claudia Villalonga, Alberto Calatron...
FCCM
2008
IEEE
165views VLSI» more  FCCM 2008»
14 years 4 months ago
Performance Analysis with High-Level Languages for High-Performance Reconfigurable Computing
High-Level Languages (HLLs) for FPGAs (FieldProgrammable Gate Arrays) facilitate the use of reconfigurable computing resources for application developers by using familiar, higher...
John Curreri, Seth Koehler, Brian Holland, Alan D....