Sciweavers

290 search results - page 15 / 58
» High-Speed MARS Hardware
Sort
View
ICCD
2004
IEEE
103views Hardware» more  ICCD 2004»
14 years 4 months ago
A Two-Layer Bus Routing Algorithm for High-Speed Boards
The increasing clock frequencies in high-end industrial circuits bring new routing challenges that can not be handled by traditional algorithms. An important design automation pro...
Muhammet Mustafa Ozdal, Martin D. F. Wong
ICCAD
2003
IEEE
154views Hardware» more  ICCAD 2003»
14 years 4 months ago
Length-Matching Routing for High-Speed Printed Circuit Boards
As the clock frequencies used in industrial applications increase, the timing requirements imposed on routing problems become tighter. So, it becomes important to route the nets w...
Muhammet Mustafa Ozdal, Martin D. F. Wong
ASYNC
2007
IEEE
154views Hardware» more  ASYNC 2007»
14 years 1 months ago
Design of a High-Speed Asynchronous Turbo Decoder
This paper explores the advantages of high performance asynchronous circuits in a semi-custom standard cell environment for high-throughput turbo coding. Turbo codes are high-perf...
Pankaj Golani, Georgios D. Dimou, Mallika Prakash,...
CEEMAS
2007
Springer
14 years 1 months ago
Collaborative Attack Detection in High-Speed Networks
We present a multi-agent system designed to detect malicious traffic in high-speed networks. In order to match the performance requirements related to the traffic volume, the net...
Martin Rehák, Michal Pechoucek, Pavel Celed...
DATE
2002
IEEE
95views Hardware» more  DATE 2002»
14 years 17 days ago
Optimal Transistor Tapering for High-Speed CMOS Circuits
Transistor tapering is a widely used technique applied to optimize the geometries of CMOS transistors in highperformance circuit design with a view to minimizing the delay of a FE...
Li Ding 0002, Pinaki Mazumder