290 search results - page 16 / 58 » High-Speed MARS Hardware |
ACSAC
2000
IEEE
14 years 21 hour ago
2000
IEEE
The performance of RSA hardware is primarily determined by an efficient implementation of the long integer modular arithmetic and the ability to utilize the Chinese Remainder The...
INFOCOM
2000
IEEE
13 years 12 months ago
2000
IEEE
-In this paper, we present a fast and scalable pipelined priority queue architecture for use in high-performance switches with support for fine-grained quality of service (QoS) gu...
ASPDAC
2007
ACM
13 years 11 months ago
2007
ACM
- The power dissipation (PT) and delay time (tdT) of a CMOS clock driver were minimized. Eight test circuits, each of which has 2 two-stage clock drivers, and a register array were...
DATE
2008
IEEE
13 years 9 months ago
2008
IEEE
We propose two crosstalk reducing coding schemes using ternary busses. In addition to low power consumption and reduced delay, our schemes offer other advantages over binary codin...
AHS
2007
IEEE
13 years 7 months ago
2007
IEEE
Online incremental evolution for a complex high-speed pattern recognition architecture has been implemented on a Xilinx Virtex-II Pro FPGA. The fitness evaluation module is entir...