140 search results - page 10 / 28 » High-level design for asynchronous logic |
ICCAD
2006
IEEE
14 years 4 months ago
2006
IEEE
This work describes a new mapping technique, RAM-MAP, that identifies parts of circuits that can be efficiently mapped into the synchronous embedded memories found on field prog...
DFT
2002
IEEE
14 years 17 days ago
2002
IEEE
Concurrent error detection (CED) methods are typically employed to provide an indication of the operational health of synchronous circuits during normal functionality. Existing CE...
DAC
2006
ACM
14 years 1 months ago
2006
ACM
Architectural decisions for DSP modules are often analyzed using high level C models. Such high-level explorations allow early examination of the algorithms and the architectural ...
ATS
2000
IEEE
14 years 1 days ago
2000
IEEE
At very high frequencies, the major potential of asynchronous circuits is absence of clock skew and, through that, better exploitation of relative timing relations. This paper pre...
DDECS
2009
IEEE
14 years 2 months ago
2009
IEEE
—Quasi Delay Insensitive asynchronous logic is a very robust system allowing safe implementations while requiring minimal timing assumptions. Unfortunately the design methodologi...