140 search results - page 15 / 28 » High-level design for asynchronous logic |
ICCAD
1999
IEEE
13 years 12 months ago
1999
IEEE
This paper describes a method of synthesis of asynchronous circuits with relative timing. Asynchronous communication between gates and modules typically utilizes handshakes to ens...
FCCM
2008
IEEE
14 years 2 months ago
2008
IEEE
—Gel is a hardware description language that enables quick scripting of high level designs and can be easily extended to new design patterns. It is expression oriented and extrem...
TCAD
2002
13 years 7 months ago
2002
With the advent of system-on-a-chip design, many application specific integrated circuits (ASICs) now require multiple design clocks that operate asynchronously to each other. This...
ASYNC
2000
IEEE
14 years 14 hour ago
2000
IEEE
Fault Abstraction and Collapsing Framework for Asynchronous Circuits Philip P. Shirvani, Subhasish Mitra Center for Reliable Computing Stanford University Stanford, CA Jo C. Eberge...
SIGSOFT
2007
ACM
14 years 8 months ago
2007
ACM
Asynchronous systems components are hard to write, hard to reason about, and (not coincidentally) hard to mechanically verify. In order to achieve high performance, asynchronous c...