1773 search results - page 11 / 355 » High-level power estimation |
VLSID
2005
IEEE
2005
IEEE
Formal Methods for Analyzing the Completeness of an Assertion Suite against a High-Level Fault Model
14 years 1 months ago
One of the emerging challenges in formal property verification (FPV) technology is the problem of deciding whether sufficient properties have been written to cover the design in...
ISLPED
2003
ACM
14 years 29 days ago
2003
ACM
This paper addresses two aspects of low-power design for FPGA circuits. First, we present an RT-level power estimator for FPGAs with consideration of wire length. The power estima...
IADIS
2004
13 years 9 months ago
2004
With rapid development of the Internet, e-learning system has become more and more popular. Currently, to solve the issue of sharing and reusing of teaching materials in different...
FP
1992
13 years 11 months ago
1992
The interface with the outside world has always been one of the weakest points of functional languages. It is not easy to incorporate I/O without being allowed to do side-effects....
CORR
2011
Springer
13 years 2 months ago
2011
Springer
Generating multimedia streams, such as in a netradio, is a task which is complex and difficult to adapt to every users’ needs. We introduce a novel approach in order to achieve i...