1773 search results - page 3 / 355 » High-level power estimation |
150
Voted
SAMOS
2004
Springer
15 years 9 months ago
2004
Springer
In recent years, power consumption has become a critical concern for many VLSI systems. Whereas several case studies demonstrate that technology-, layout-, and gate-level technique...
143
Voted
CVPR
2011
IEEE
14 years 11 months ago
2011
IEEE
With the rise in popularity of digital cameras, the amount of visual data available on the web is growing exponentially. Some of these pictures are extremely beautiful and aesthet...
130
Voted
DATE
2008
IEEE
15 years 10 months ago
2008
IEEE
— The worst-case delay/power of function units has been used in traditional high level synthesis to facilitate design space exploration. As technology scales to nanometer regime,...
121
Voted
DATE
2003
IEEE
15 years 9 months ago
2003
IEEE
We present a high-level synthesis algorithm solving the combined scheduling, allocation and binding problem minimizing area under both latency and maximum power per clock-cycle co...
98
Voted
ESTIMEDIA
2006
Springer
15 years 7 months ago
2006
Springer
