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IPPS
1995
IEEE
14 years 2 months ago
The RACE network architecture
The RACE R parallel computer system provides a highperformance parallel interconnection network at low cost. This paper describes the architecture and implementation of the RACE ...
Bradley C. Kuszmaul
ISPA
2007
Springer
14 years 4 months ago
Parallelization Strategies for the Points of Interests Algorithm on the Cell Processor
The Cell processor is a typical example of a heterogeneous multiprocessor-on-chip architecture that uses several levels of parallelism to deliver high performance. Closing the gap ...
Tarik Saidani, Lionel Lacassagne, Samir Bouaziz, T...
ASAP
2006
IEEE
127views Hardware» more  ASAP 2006»
14 years 16 days ago
A Cost Effective Pipelined Divider for Double Precision Floating Point Number
Abstract--The growth of high-performance application in computer graphics, signal processing and scientific computing is a key driver for high performance, fixed latency, pipelined...
Sandeep B. Singh, Jayanta Biswas, S. K. Nandy
CATA
2003
13 years 12 months ago
Load Balancing Strategies for Multi-Block Overset Grid Applications
The multi-block overset grid method is a powerful technique for high-fidelity computational fluid dynamics (CFD) simulations about complex aerospace configurations. The solutio...
M. Jahed Djomehri, Rupak Biswas, Noé Lopez-...
DSRT
2006
IEEE
14 years 4 months ago
Grid-enabling FIRST: Speeding Up Simulation Applications Using WinGrid
The vision of grid computing is to make computational power, storage capacity, data and applications available to users as readily as electricity and other utilities. Grid infrast...
Navonil Mustafee, Anders Alstad, Bjorn Larsen, Sim...