24 search results - page 3 / 5 » High-speed VLSI architecture for parallel Reed-Solomon decod... |
ASYNC
2003
IEEE
14 years 19 days ago
2003
IEEE
We present a high-speed, clockless, serial link transceiver for inter-chip communication in asynchronous VLSI systems. Serial link transceivers achieve high offchip data rates by ...
ISCAS
2011
IEEE
12 years 11 months ago
2011
IEEE
—We propose a multi-layer parallel decoding algorithm and VLSI architecture for decoding of structured quasi-cyclic low-density parity-check codes. In the conventional layered de...
GLVLSI
2007
IEEE
14 years 1 months ago
2007
IEEE
Parallel counters are key elements in many arithmetic circuits, especially fast multipliers. In this paper, novel architectures and designs for high speed, low power (3, 2), (7, 3...
CORR
2010
Springer
13 years 7 months ago
2010
Springer
Fixed-complexity sphere decoder (FSD) is a recently proposed technique for multiple-input multiple-output (MIMO) detection. It has several outstanding features such as constant thr...
ISLPED
2003
ACM
14 years 18 days ago
2003
ACM
Presented in this paper is a low-power architecture for turbo decodings of parallel concatenated convolutional codes. The proposed architecture is derived via the concept of block...