48 search results - page 3 / 10 » Highly pipelined asynchronous FPGAs |
FPGA
1999
ACM
13 years 12 months ago
1999
ACM
Pipelining of data path structures increases the throughput rate at the expense of enlarged resource usage and latency unless architectures optimized towards specific applications...
CF
2004
ACM
14 years 1 months ago
2004
ACM
This paper presents a fault tolerant design technique for the clockless wave pipeline. The specific architectural model investigated in this paper is the two-phase clockless asyn...
FCCM
2006
IEEE
14 years 1 months ago
2006
IEEE
FPGAs are becoming more and more attractive for high precision scientific computations. One of the main problems in efficient resource utilization is the quadratically growing r...
ERSA
2004
13 years 9 months ago
2004
In this paper, we propose an architecture for floatingpoint based LU decomposition for large-sized matrices. Our proposed architecture is based on the well known concept of blocki...
DFT
2003
IEEE
14 years 28 days ago
2003
IEEE
This paper proposes a new fault model and its modeling and analysis methods in a clockless asynchronous wave pipeline for extensive yield evaluation and assurance. It is highly de...