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DATE
2007
IEEE
134views Hardware» more  DATE 2007»
15 years 10 months ago
Non-fractional parallelism in LDPC decoder implementations
Because of its excellent bit-error-rate performance, the Low-Density Parity-Check (LDPC) decoding algorithm is gaining increased attention in communication standards and literatur...
John Dielissen, Andries Hekstra
ASPDAC
2011
ACM
193views Hardware» more  ASPDAC 2011»
14 years 7 months ago
A structured parallel periodic Arnoldi shooting algorithm for RF-PSS analysis based on GPU platforms
The recent multi/many-core CPUs or GPUs have provided an ideal parallel computing platform to accelerate the timeconsuming analysis of radio-frequency/millimeter-wave (RF/ MM) int...
Xuexin Liu, Hao Yu, Jacob Relles, Sheldon X.-D. Ta...
DEBS
2010
ACM
15 years 7 months ago
Evaluation of streaming aggregation on parallel hardware architectures
We present a case study parallelizing streaming aggregation on three different parallel hardware architectures. Aggregation is a performance-critical operation for data summarizat...
Scott Schneider, Henrique Andrade, Bugra Gedik, Ku...
SPAA
2010
ACM
15 years 8 months ago
Simplifying concurrent algorithms by exploiting hardware transactional memory
We explore the potential of hardware transactional memory (HTM) to improve concurrent algorithms. We illustrate a number of use cases in which HTM enables significantly simpler c...
Dave Dice, Yossi Lev, Virendra J. Marathe, Mark Mo...
ISLPED
2010
ACM
206views Hardware» more  ISLPED 2010»
15 years 4 months ago
Energy efficient implementation of parallel CMOS multipliers with improved compressors
Booth encoding is believed to yield faster multiplier designs with higher energy consumption. 16x16-bit Booth and NonBooth multipliers are analyzed in energy and delay space under...
Dursun Baran, Mustafa Aktan, Vojin G. Oklobdzija