2200 search results - page 403 / 440 » Hop Integrity in Computer Networks |
102
Voted
INFOCOM
1996
IEEE
15 years 6 months ago
1996
IEEE
This report analyzes two popular heuristics for ensuring packet integrity in ATM switching systems. In particular, we analyze the behavior of packet tail discarding, in order to u...
101
Voted
CEC
2009
IEEE
15 years 6 months ago
2009
IEEE
This paper presents a new unified design flow developed within the Perplexus project that aims to accelerate parallelizable data-intensive applications in the context of ubiquitous...
149
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VLSID
2010
IEEE
15 years 6 months ago
2010
IEEE
Network-on-Chip combined with Globally Asynchronous Locally Synchronous paradigm is a promising architecture for easy IP integration and utilization with multiple voltage levels. ...
129
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GLVLSI
2009
IEEE
15 years 6 months ago
2009
IEEE
A methodology is proposed to efficiently estimate the substrate noise generated by large scale aggressor circuits. Small spatial voltage differences within the ground distribution...
129
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CODES
2006
IEEE
15 years 6 months ago
2006
IEEE
During System on Chip (SoC) design, Network on Chip (NoC) prototyping is used for adapting NoC parameters to the application running on the chip. This prototyping is currently don...