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ISQED
2007
IEEE
165views Hardware» more  ISQED 2007»
14 years 1 months ago
On-Line Adjustable Buffering for Runtime Power Reduction
We present a novel technique to exploit the power-performance tradeoff. The technique can be used stand-alone or in conjunction with dynamic voltage scaling, the mainstream techn...
Andrew B. Kahng, Sherief Reda, Puneet Sharma
ISPD
2004
ACM
146views Hardware» more  ISPD 2004»
14 years 25 days ago
Power-aware clock tree planning
Modern processors and SoCs require the adoption of poweroriented design styles, due to the implications that power consumption may have on reliability, cost and manufacturability ...
Monica Donno, Enrico Macii, Luca Mazzoni
FPL
2010
Springer
124views Hardware» more  FPL 2010»
13 years 5 months ago
Finding System-Level Information and Analyzing Its Correlation to FPGA Placement
One of the more popular placement algorithms for Field Programmable Gate Arrays (FPGAs) is called Simulated Annealing (SA). This algorithm tries to create a good quality placement ...
Farnaz Gharibian, Lesley Shannon, Peter Jamieson
ISCA
2007
IEEE
171views Hardware» more  ISCA 2007»
14 years 1 months ago
Power provisioning for a warehouse-sized computer
Large-scale Internet services require a computing infrastructure that can be appropriately described as a warehouse-sized computing system. The cost of building datacenter facilit...
Xiaobo Fan, Wolf-Dietrich Weber, Luiz André...
TAP
2008
Springer
102views Hardware» more  TAP 2008»
13 years 7 months ago
Visualizing graphs in three dimensions
It has been known for some time that larger graphs can be interpreted if laid out in 3D and displayed with stereo and/or motion depth cues to support spatial perception. However, ...
Colin Ware, Peter Mitchell