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MICRO
2005
IEEE
126views Hardware» more  MICRO 2005»
14 years 2 months ago
Cost Sensitive Modulo Scheduling in a Loop Accelerator Synthesis System
Scheduling algorithms used in compilers traditionally focus on goals such as reducing schedule length and register pressure or producing compact code. In the context of a hardware...
Kevin Fan, Manjunath Kudlur, Hyunchul Park, Scott ...
MSWIM
2005
ACM
14 years 2 months ago
Topology control with better radio models: implications for energy and multi-hop interference
Topology Control (TC) is a well-studied technique used in wireless ad hoc networks to find energy-efficient and/or low-interference subgraphs of the maxpower communication graph....
Douglas M. Blough, Mauro Leoncini, Giovanni Resta,...
VRML
2004
ACM
14 years 2 months ago
PathSim visualizer: an Information-Rich Virtual Environment framework for systems biology
Increasingly, biology researchers and medical practitioners are using computational tools to model and analyze dynamic systems across scales from the macro to the cellular to the ...
Nicholas F. Polys, Doug A. Bowman, Chris North, Re...
FPGA
2004
ACM
121views FPGA» more  FPGA 2004»
14 years 2 months ago
Divide and concatenate: a scalable hardware architecture for universal MAC
We present a cryptographic architecture optimization technique called divide-and-concatenate based on two observations: (i) the area of a multiplier and associated data path decre...
Bo Yang, Ramesh Karri, David A. McGrew
CP
2003
Springer
14 years 2 months ago
Incremental Computation of Resource-Envelopes in Producer-Consumer Models
Abstract. Interleaved planning and scheduling employs the idea of extending partial plans by regularly heeding to the scheduling constraints during search. One of the techniques us...
T. K. Satish Kumar
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