121 search results - page 12 / 25 » Hybrid cache architecture with disparate memory technologies |
ARCS
2009
Springer
14 years 1 months ago
2009
Springer
The disparity between microprocessor clock frequencies and memory latency is a primary reason why many demanding applications run well below peak achievable performance. Software c...
MICRO
2006
IEEE
14 years 22 days ago
2006
IEEE
One of the major issues faced by the semiconductor industry today is that of reducing chip yields. As the process technologies have scaled to smaller feature sizes, chip yields ha...
RTAS
1997
IEEE
13 years 11 months ago
1997
IEEE
3rd IEEE Real-time Technology and Applications Symposium (RTAS), June 1997 in Montreal, Canada Cache-partitioning techniques have been invented to make modern processors with an e...
RTAS
2005
IEEE
14 years 9 days ago
2005
IEEE
While caches have become invaluable for higher-end architectures due to their ability to hide, in part, the gap between processor speed and memory access times, caches (and partic...
ISCA
2005
IEEE
14 years 9 days ago
2005
IEEE
Recent I/O technologies such as PCI-Express and 10Gb Ethernet enable unprecedented levels of I/O bandwidths in mainstream platforms. However, in traditional architectures, memory ...