121 search results - page 24 / 25 » Hybrid cache architecture with disparate memory technologies |
CASES
2008
ACM
13 years 9 months ago
2008
ACM
While technology advances have made MPSoCs a standard architecture for embedded systems, their applicability is increasingly being challenged by dramatic increases in the amount o...
CIKM
2006
Springer
13 years 11 months ago
2006
Springer
We propose to adapt the newly emerged cache-oblivious model to relational query processing. Our goal is to automatically achieve an overall performance comparable to that of fine-...
MICRO
2010
IEEE
13 years 5 months ago
2010
IEEE
As the number of cores and threads in manycore compute accelerators such as Graphics Processing Units (GPU) increases, so does the importance of on-chip interconnection network des...
VRML
2004
ACM
14 years 23 days ago
2004
ACM
In this paper we present a VRML97-X3D extension to describe precomputed visibility relationships in the context of progressive transmission as well as real time visualization of m...
HPCA
2005
IEEE
14 years 7 months ago
2005
IEEE
Improvements in semiconductor technology now enable Chip Multiprocessors (CMPs). As many future computer systems will use one or more CMPs and support shared memory, such systems ...