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CDES
2006
158views Hardware» more  CDES 2006»
13 years 10 months ago
A Double Precision Floating Point Multiplier Suitably Designed for FPGAs and ASICs
In this paper, a double precision IEEE 754 floating-point multiplier with high speed and low power is presented. The bottleneck of any double precision floatingpoint multiplier des...
Himanshu Thapliyal, Vishal Verma, Hamid R. Arabnia
CHES
2007
Springer
327views Cryptology» more  CHES 2007»
14 years 2 months ago
On the Power of Bitslice Implementation on Intel Core2 Processor
Abstract. This paper discusses the state-of-the-art fast software implementation of block ciphers on Intel’s new microprocessor Core2, particularly concentrating on “bitslice i...
Mitsuru Matsui, Junko Nakajima
FCCM
2009
IEEE
147views VLSI» more  FCCM 2009»
14 years 13 days ago
FPGA Accelerated Simulation of Biologically Plausible Spiking Neural Networks
Artificial neural networks are a key tool for researchers attempting to understand and replicate the behaviour and intelligence found in biological neural networks. Software simul...
David Thomas, Wayne Luk
JCP
2006
128views more  JCP 2006»
13 years 8 months ago
A Service Oriented Framework for Multimedia Radio Networks
- In order to enable fast deployment of new emerging services over multimedia radio networks, it is important to design an efficient service-based platform with necessary traffic m...
Asma Ben Letaifa, Sami Tabbane, Zièd Chouka...
CODES
2005
IEEE
14 years 2 months ago
Dynamic phase analysis for cycle-close trace generation
For embedded system development, several companies provide cross-platform development tools to aid in debugging, prototyping and optimization of programs. These are full system em...
Cristiano Pereira, Jeremy Lau, Brad Calder, Rajesh...