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» ILP-based optimization of sequential circuits for low power
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DATE
2005
IEEE
123views Hardware» more  DATE 2005»
14 years 3 months ago
Low Power Oriented CMOS Circuit Optimization Protocol
Alexandre Verle, Xavier Michel, Nadine Azém...
ICCAD
1995
IEEE
96views Hardware» more  ICCAD 1995»
14 years 1 months ago
Delay optimal partitioning targeting low power VLSI circuits
Hirendu Vaishnav, Massoud Pedram
GLVLSI
2006
IEEE
112views VLSI» more  GLVLSI 2006»
14 years 3 months ago
A design methodology for temperature variation insensitive low power circuits
Operating an integrated circuit at the prescribed nominal supply voltage is not preferable for reliable circuit operation under temperature fluctuations. A design methodology base...
Ranjith Kumar, Volkan Kursun
CORR
2002
Springer
93views Education» more  CORR 2002»
13 years 9 months ago
Synthesis of Low-Power Digital Circuits Derived from Binary Decision Diagrams
-- This paper introduces a novel method for synthesizing digital circuits derived from Binary Decision Diagrams (BDDs) that can yield to reduction in power dissipation. The power r...
Denis V. Popel
ISLPED
1999
ACM
177views Hardware» more  ISLPED 1999»
14 years 2 months ago
Low power synthesis of dual threshold voltage CMOS VLSI circuits
The use of dual threshold voltages can significantly reduce the static power dissipated in CMOS VLSI circuits. With the supply voltage at 1V and threshold voltage as low as 0.2V ...
Vijay Sundararajan, Keshab K. Parhi