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ERSA
2006
161views Hardware» more  ERSA 2006»
13 years 8 months ago
A Parametric Study of Scalable Interconnects on FPGAs
Abstract-- With the constantly increasing gate capacity of FPGAs, a single FPGA chip is able to employ large-scale applications. To connect a large number of computational nodes, N...
Daihan Wang, Hiroki Matsutani, Masato Yoshimi, Mic...
AICT
2009
IEEE
123views Communications» more  AICT 2009»
14 years 13 days ago
Performance Evaluation of Multicast Routing over Multilayer Multistage Interconnection Networks
Multilayer MINs have emerged mainly due to the increased need for routing capacity in the presence of multicast and broadcast traffic, their performance prediction and evaluation ...
D. C. Vasiliadis, G. E. Rizos, C. Vassilakis, E. G...
ANCS
2007
ACM
13 years 11 months ago
Experimental evaluation of a coarse-grained switch scheduler
Modern high performance routers rely on sophisticated interconnection networks to meet ever increasing demands on capacity. Previous studies have used a combination of analysis an...
Charlie Wiseman, Jonathan S. Turner, Ken Wong, Bra...
CODES
2003
IEEE
14 years 18 days ago
A modular simulation framework for architectural exploration of on-chip interconnection networks
Ever increasing complexity and heterogeneity of SoC platforms require diversified on-chip communication schemes beyond the currently omnipresent shared bus architectures. To prev...
Tim Kogel, Malte Doerper, Andreas Wieferink, Raine...
MICRO
2002
IEEE
171views Hardware» more  MICRO 2002»
14 years 7 days ago
Orion: a power-performance simulator for interconnection networks
With the prevalence of server blades and systems-ona-chip (SoCs), interconnection networks are becoming an important part of the microprocessor landscape. However, there is limite...
Hangsheng Wang, Xinping Zhu, Li-Shiuan Peh, Sharad...