374 search results - page 24 / 75 » IP = PSPACE using Error Correcting Codes |
DFT
2009
IEEE
14 years 2 months ago
2009
IEEE
Hybrid CMOS/non-CMOS memories, in short hybrid memories, have been lauded as future ultra-capacity data memories. Nonetheless, such memories are going to suffer from high degree o...
ISCAS
2006
IEEE
14 years 1 months ago
2006
IEEE
— In this paper, the performance of an exponentially modulated filter bank based multicarrier (FBMC) modulation is compared with a cyclic prefix based OFDM (CP-OFDM). Both fram...
VLSID
2005
IEEE
14 years 1 months ago
2005
IEEE
In this paper, we have proposed a design technique for the reversible circuit of Binary Coded Decimal (BCD) adder. The proposed circuit has the ability to add two 4bits binary var...
ICCAD
2007
IEEE
14 years 4 months ago
2007
IEEE
Abstract— Nanoscale technology promises dramatically increased device density, but also decreased reliability. With bit error rates projected to be as high as 10%, designing a us...
OOPSLA
2005
Springer
14 years 1 months ago
2005
Springer
A number of effective error detection tools have been built in recent years to check if a program conforms to certain design rules. An important class of design rules deals with s...